The main intent of this paper is to design and implementation of novel hybrid Multiplier design at high speed and low delay applications. Basically, the implementation of hybrid Multiplier is based in VLSI chips because they are used as critical element. In the same way partial product generator is used in the multiplier to generate the propagator and generator signals. While designing dual partial product unit, optimized multiplier are used most widely. The novel hybrid Multiplier uses adequate hardware implementation. The transistor logic system only depends on the novel hybrid Multiplier to reduce the delay. Hence compared to adder system, the novel hybrid Multiplier systems gives effective results in terms of speed, area and delay.

Novel Hybrid Multiplier, VLSI, CMOS, Hybrid adder, Partial products, Multiplier, Multiplicand, Carry generation unit.