This paper describes three different designs of a full adder based on adiabatic logic. The first design (A-I) uses parallel computing to reduce the delay time, while the second design (A-II) uses two-phase clocked adiabatic static complementary metal oxide logic to decrease power dissipation. The third design (A-III) uses parallel computing for both sum and carry generation and introduces a buffer to restore the logic level. The results of the designs are compared to previous approaches, and it is found that A-II and A-III show significant improvements in power delay product (PDP) compared to other designs. Additionally, the designs perform well under varied temperature conditions and are energy-efficient for low power applications. Overall, the proposed designs show promise for improving the performance and energy efficiency of full adders, particularly for low power applications. The use of adiabatic logic and parallel computing techniques are effective in reducing delay time and power dissipation, respectively.

Adiabatic logic · Energy efficiency · Low power adder · Parallel computing · Power delay product