In CMOS circuits more power is dissipated during charging and discharging the load capacitance. This can be lowered by minimizing the number of transitions inside CMOS circuit. This paper includes efficient encoding technique to reduce the transition activity. An Adaptive Encoding technique is one among all available methods. To reduce the power of interchip interconnects, an adaptive encoding scheme called adaptive word reordering (AWR) is proposed, which effectively decreases the number of signal transitions, leading to a significant power reduction. A novel circuit is implemented, which exploits the time domain to represent complex bit transition computations as delays and, thus, limits the power overhead due to encoding. The effectiveness of AWR is validated in terms of decrease in both bit transitions and power consumption. As an extension of this concept, Gate Diffusion Input based architectures are introduced to design proposed encoding process in order to reduce power constraints.

adaptive word reordering, Gate diffusion Input, signal transitions, Latency, Interconnect.