This paper presents a novel design of reversible logic based Arithmetic Logic Unit (ALU) which is efficient in comparison to the irreversible design in terms of power and area. In reversible logic design each input is mapped to a particular output therefore each output is known which prevent bit loss and reduces the power dissipation. The design ALU is simulated using Xilinx 2019.1 for logical verification. Further the design is synthesized and power comparison is done for both the reversible and irreversible ALU. It is observed that dynamic logic power is reduced by 53% and area by 20%.

Reversible logic, garbage output, dynamic power.