A full adder is a crucial part of designing many digital systems and it is utilised in many different applications, including digital signal processors, microprocessors, and microcontrollers. Electronic devices and circuits require great control, which calls for low power and high speed. The current paper serves as an example of the importance of power, delay, and transistor count in this context. In this paper a low power and high performance 1-bit full adder cell is implemented based on gate diffusion input (GDI). The delay, power, power delay product (PDP) are extracted and compared for the proposed full adder cell with other widely used full adders. For all varieties of full adders, we discover that the GDI approach effectively lowers power usage. However, compared to the CFA design, the MFA and HFA designs are slightly more delayed. The average power dissipation of proposed adder is about 83.2 pWatts at operational voltage of 1V. The next two adders which performed better are 12T and 10T GDI full adders with PDP of 2.7fj and 1.8fj. The proposed Hybrid Full Adder gives out lower PDP of 2.07aj than other adders. The performance of the proposed circuits was examined using Cadence Virtuoso tool at 1 V supply voltage with 45nm technology.

CMOS, Full Adder, Gate Diffusion Input (GDI), MGDI, Memory Cell.