Numerous applications of Finite Impulse Response (FIR) Filter have been found in many signal processing applications, biomedical applications, de-noising, etc., It is essential to design the FIR filter with high speed and low power consumption. In this proposed work, design of FIR filter has been made with RCPA. In this paper a reverse carry propagate adder (RCPA) is presented. In the RCPA structure, the carry signal propagates in a counter-flow manner from the most significant bit to the least significant bit; hence, the carry input signal has higher significance than the output carry. This method of carry propagation leads to higher stability in the presence of delay variations. Three implementations of the reverse carry propagate full-adder (RCPFA) cell with different delay, power, energy, and accuracy levels are introduced. The best one is selected and implemented in FIR filter. The proposed structure may be combined with an exact carry adder to form hybrid adders with tunable levels of accuracy. This Proposed RCPFA System Implemented using Verilog and Simulated by ModelSim 6.4a and Synthesized by Xilinx ISE 9.1i tool.

AOI- AND OR Invert, OAI – OR AND Invert , LUT – Look Up Table, RTL – Register Transistor Logic, DCT – Discrete Cosine Transform, DWT – Discrete Wave Transform