The high speed potential of I.C.components can be exploited by shortening the pipeline clock period. Although there are some factors which dominate the shortening,the design of an experimental computer employs the principle of maximum time difference at the system level to determine the clock period and the integrated consideration of architecture,logic design and engineering layout to achieve a system clock period of 9.8 ns using conventional ECL chips of 2ns gate delay.The multiplier in this model,which i…

Kung s reasoning procedure is characterized by high parallelism in the sense that an unlimited number of CPUs can be used to carry out the computation in parallel.This paper presents a proof of the soundness and completeness of the reasoning procedure based on Herbrand s theorem.

This paper describes the theory and implementation of a testability measure program called RFOTM.It is suggested that the real difficulty in test generation should be reflected in testability measure.We analyse the behavior of fanout and reconvergent fanout which cause inconsistency in generating tests.A classification of fanouts is given and a class of fanouts which behaves like fanout-free lines is described. Based on this observation,the new measure is developed with emphasis on the influence of fanout a…

Program slicing is a method for automatical program decomposition.This paper presents an improved slicing algorithm on the basis of static analysis of the control structure of loop statements.The slice obtained by the new algorithm is guaranteed to be no larger than that obtained by the previous slicing algorithm developed by Mark Weiser.Moreover,the former will be much smaller than the latter for certain kinds of programs.In addition,a brief discussion of using slicing in program verification has been give…

The development of systems software in functional programming language is still an open problem. This paper describes a preliminary experiment with systems programming in Backus FP systems.It consists of two systems programs.One is a self-compiler of FP,the other an interpreter of the semantics of FFP(Formal Functional Programming).Both were implemented on an FP machine——FPM2.Some discussions are made finally.

With an example,this paper describes a method of using temporal logic for stepwise analysis of protocol specifications.Each level in the specified hierarchy is a kind of incarnation from higher-levels by adding some implementation strategies,and the correctness of top-down refinements could be verified in the unified temporal framework.

A necessary condition for a self-synchronizing delayless invertible finite state machine(FSM)being a scrambler was conjectured in[1].A counterexample to the conjecture is given in this paper.

ZGLI,an office automation system for municipal administration,is presented.It is a distributed microcomputer system based on OMNINET.Each node of it is an IBM PC/XT microcomputer with Chinese character facilities.The system consists of a distributed database management system,a Chinese character electronic mail system,a Chinese word processor and others.Its functions include document management, report form management,research project management,finance management and information access.