With the rise of mobile devices, power consumption has become a pivotal design parameter in digital circuits. The primary contributor to power dissipation during idle mode is leakage currents, which have seen a significant increase due to threshold voltage scaling and the scaling of oxide thickness. As mobile devices predominantly operate in standby mode, minimizing leakage power during this state is crucial for prolonging battery life. This has made low power design a paramount consideration in CMOS circuit design. As we investigate into nanometer scales, power dissipation accounts for approximately 35% of chip power, potentially limiting chip functionality. This paper research into the major power dissipation mechanisms in digital logic circuits, emphasizing the exponential rise in sub-threshold leakage current due to reductions in the threshold voltage of MOS transistors. Various techniques to mitigate sub-threshold leakage, such as source biasing, stack technique, and multi-threshold CMOS (MTCMOS) technique, are discussed. Notably, while MTCMOS and super cutoff CMOS (SCCMOS) techniques are prevalent, they still exhibit considerable standby leakage power dissipation. This underscores the need for innovative circuit design techniques to further diminish standby leakage power consumption.

Multi-threshold CMOS (MTCMOS), Super Cutoff CMOS (SCCMOS) Technique, CMOS Circuits