Bimonthly    Since 1986
ISSN 1004-9037
Publication Details
Edited by: Editorial Board of Journal of Data Acquisition and Processing
P.O. Box 2704, Beijing 100190, P.R. China
Sponsored by: Institute of Computing Technology, CAS & China Computer Federation
Undertaken by: Institute of Computing Technology, CAS
Published by: SCIENCE PRESS, BEIJING, CHINA
Distributed by:
China: All Local Post Offices
 
   
      1 Jan 2023, Volume 38 Issue 1   
    Article

    1. EFFECTIVE DESIGN OF COMBINATIONAL HALF-ADDER AND SUBTRACTOR CIRCUITS DESIGN BASED ON NANOELECTRONICS USING QCA TECHNOLOGY
    Dilip Kumar Sharma1, Prachi Goyal2*, Praveen Kumar Patidar3, Suyog Munshi4, Pranav Paranjpe5 Mangukiya Hiteshkumar Bhupatbhai 6
    Journal of Data Acquisition and Processing, 2023, 38 (1): 2582-2591 . 

    Abstract

    Quantum dot Cellular Automata (QCA) is a novel and potentially attractive technology for implementing computing architectures at the Nano-scale. The basic Boolean primitive in QCA is the majority gate. The Quantum Devices for Advanced Nano-electronic Technology project work is the development of a technology for the implementation of different logic circuits based on Quantum Cellular Automata (QCA) architecture. QCA cells characterized by two possible polarization states. The logical structures using QCA has been designed and tested using QCA Designer software. The operation of the structures has been verified according to the truth table. Quantum-dot cellular automata is a novel nanoelectronics nanotechnology that promises very smaller size of digital circuits, very low power consumption, with high speed, minimum delay and operation at Thz (Tera-Hertz) frequencies are highly desired features in the design and fabrication of digital logic circuits. It is considered as a resolution to the scaling problems in CMOS (complementary metal oxide semiconductor) technology. In this paper investigates the quantum-dot cellular automata technology as an alternative to conventional CMOS technology for implementing the nano-scale half adder and half subtractor circuits. The proposed design is proved to be efficient in term of minimum cell count, minimum area in 〖μm〗^2, low delay from input to output and circuits complexity. The proposed design simulated by using QCADesigner tool V. 2.0.3. The simulated results were verified according to the truth table.

    Keyword

    Majority Gate, Nanotechnology, Nanoelectronics, Quantum-dot cellular automata, Half-adder, Half-Subtractor.


    PDF Download (click here)

SCImago Journal & Country Rank

ISSN 1004-9037

         

Home
Editorial Board
Author Guidelines
Subscription
Journal of Data Acquisition and Processing
Institute of Computing Technology, Chinese Academy of Sciences
P.O. Box 2704, Beijing 100190 P.R. China
E-mail: info@sjcjycl.cn
 
  Copyright ©2015 JCST, All Rights Reserved